U.S. application Ser. No. 20020028541 which was filed as U.S. application Ser. No. 09/927,648, on Aug. 13, 2001 and which is incorporated by reference in its entirety, discloses a monolithic three dimensional array of charge storage devices. In one embodiment in this application, the charge storage devices of the array comprise both top gate staggered and inverted (i.e., bottom gate) staggered thin film transistors. Thin film transistors are called “staggered” when the gate electrode is located on the opposite side of the active layer from the source and drain electrodes.
The charge storage thin film transistors in the array store charge in charge storage regions, such as in dielectric isolated floating gates or in a so called “ONO” (oxide-nitride-oxide) film or stack. The floating gate is separated from the channel region by a silicon oxide tunneling layer and is separated from the control gate by a silicon oxide blocking layer. Likewise, the silicon nitride change storage layer in an ONO film or stack is located between a silicon oxide tunneling layer and a silicon oxide blocking layer.
In a top gate transistor, where the gate electrode is located above the channel region, a high quality tunneling silicon oxide layer is formed by thermally growing the silicon oxide layer on the channel region. This thermal oxide is formed by exposing a silicon channel region to a dry or wet oxygen containing atmosphere, and-converting a top portion of the silicon channel region to a silicon oxide layer. However, in a bottom gate thin film transistor, this thermal silicon dioxide cannot be grown on the channel region because the tunneling layer is located below the channel region. Thus, the silicon dioxide tunneling layer has to be deposited on the nitride charge storage layer of the ONO charge storage region using a silicon oxide deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), such as sputtering, or atomic layer deposition (ALD) methods.